1. Field of the Invention
The present invention relates to a phase adjustment circuit for adjusting the phase relationship between a pair of clock signals.
2. Description of the Related Art
Some integrated circuits include a central processing unit (CPU) that needs to receive two clock signals having different frequencies and a predetermined phase relationship. For example, it may be necessary for all transitions of the lower-frequency clock signal to occur when the higher-frequency clock signal is in a specified (high or low) state. Although it is an easy matter to generate two clock signals satisfying this type of condition, the phase relationship between the clock signals may be altered by, for example, different propagation delays on the clock signal supply paths, so that by the time the clock signals reach the CPU, the necessary relationship may no longer obtain.
This problem is not unlike the problem of ensuring that the transitions in a data signal take place while a clock signal is in a specified state. Japanese Unexamined Patent Application Publication No. 2002-339366 discloses a phase adjustment circuit that receives a data signal DATAI and a clock signal CLKI, adjusts the phase of the clock signal CLKI so as to generate a clock signal CLKO having a desired timing relationship to the data signal DATAI, and outputs this clock signal CLKO together with the data signal DATAO.
In the disclosed phase adjustment circuit, a pair of transition monitoring circuits, operating on a system clock, detect transitions in the clock signal CLKI and data signal DATAI. A CLKI transition resets a counter that counts cycles of the system clock. A DATAI transition causes a register to latch the count value output by the counter. A delay circuit generates delayed clock signals in a plurality of delay patterns from clock signal CLKI. The delayed clock signals are input to a selector. The count value latched by the register is supplied to a circuit that generates a selection signal designating an optimum one of the delayed clock signals generated by the delay circuit. The selection signal is supplied to the selector, which selects the designated delayed clock signal and outputs it as clock signal CLKO.
For this conventional phase adjustment circuit to work, the delayed clock signals must have precisely predetermined delay times, but in practice, the delay times cannot be precisely predetermined, because they may vary due to inevitable fabrication variations in delay elements, and to variations in environmental conditions such as temperature or supply voltage. Because the selection signal is generated without regard to such variations in the delayed clock signals, there is no guarantee that the output clock signal CLKO will actually be the optimal clock signal.